Google TPU: upcoming dates

Recent

• Semiconductors11/08/2026@ChipDesk

  Google Announces TPU 8i for Low-Latency AI Inference

  Googleplex, Mountain View, California, United States (company headquarters)Google

  

  Starts 04/22/2026CONFIRMEDDate confidence: CONFIRMEDStated as firmHow firmly the source words the date: confirmed, scheduled, estimated, delayed or unverified.Show all CONFIRMED pins95% CONFIDENCEOverall confidence: 95%How well the pin's source and references back up its dates.Weighted average of how firmly 6 references, the source included, support the pin's start and end times; a reference counts half as much for every 180 days older than the newestShow all pins at 75% confidence or better200 days ago

  Dated Google^[2][3] announcement; commercialization milestones are recorded separately in the sourced timeline.

  Google announces its inference-focused eighth-generation TPU, combining 288 GB of HBM, 384 MB of on-chip SRAM and Boardfly networking across up to 1,152 chips. Availability is still listed as coming soon.

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• Semiconductors11/08/2026@ChipDesk

  Google Announces TPU 8t for Frontier AI Training

  Googleplex, Mountain View, California, United States (company headquarters)Google

  

  Starts 04/22/2026CONFIRMEDDate confidence: CONFIRMEDStated as firmHow firmly the source words the date: confirmed, scheduled, estimated, delayed or unverified.Show all CONFIRMED pins95% CONFIDENCEOverall confidence: 95%How well the pin's source and references back up its dates.Weighted average of how firmly 6 references, the source included, support the pin's start and end times; a reference counts half as much for every 180 days older than the newestShow all pins at 75% confidence or better200 days ago

  Dated Google^[1][3] announcement; commercialization milestones are recorded separately in the sourced timeline.

  Google announces the training-focused half of its eighth TPU generation: 9,600-chip superpods, native FP4, 216 GB of HBM per chip and Axion hosts. The current product page lists it as coming soon.

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• Semiconductors11/08/2026@ChipDesk

  Google Unveils Ironwood, Its Seventh-Generation TPU

  Googleplex, Mountain View, California, United States (company headquarters)Google

  

  Starts 04/09/2025CONFIRMEDDate confidence: CONFIRMEDStated as firmHow firmly the source words the date: confirmed, scheduled, estimated, delayed or unverified.Show all CONFIRMED pins95% CONFIDENCEOverall confidence: 95%How well the pin's source and references back up its dates.Weighted average of how firmly 6 references, the source included, support the pin's start and end times; a reference counts half as much for every 180 days older than the newestShow all pins at 75% confidence or better1.6 years ago

  Dated Google^[2][3] announcement; commercialization milestones are recorded separately in the sourced timeline.

  Google announces Ironwood for large-scale inference, later documented as TPU7x for both training and inference, with 192 GiB of HBM per chip and pods of up to 9,216 chips.

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• Semiconductors11/08/2026@ChipDesk

  Google Unveils Trillium, Its Sixth-Generation TPU

  Googleplex, Mountain View, California, United States (company headquarters)Google

  

  Starts 05/14/2024CONFIRMEDDate confidence: CONFIRMEDStated as firmHow firmly the source words the date: confirmed, scheduled, estimated, delayed or unverified.Show all CONFIRMED pins95% CONFIDENCEOverall confidence: 95%How well the pin's source and references back up its dates.Weighted average of how firmly 7 references, the source included, support the pin's start and end times; a reference counts half as much for every 180 days older than the newestShow all pins at 75% confidence or better2.5 years ago

  Dated Google^[1][2][3][4] announcement; commercialization milestones are recorded separately in the sourced timeline.

  Google announces Trillium (TPU v6e), with 4.7 times the peak compute per chip of TPU v5e, double its HBM capacity and a claimed improvement of over 67% in energy efficiency.

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• Semiconductors11/08/2026@ChipDesk

  Google Announces TPU v5p and the AI Hypercomputer

  Googleplex, Mountain View, California, United States (company headquarters)Google

  

  Starts 12/06/2023CONFIRMEDDate confidence: CONFIRMEDStated as firmHow firmly the source words the date: confirmed, scheduled, estimated, delayed or unverified.Show all CONFIRMED pins95% CONFIDENCEOverall confidence: 95%How well the pin's source and references back up its dates.Weighted average of how firmly 5 references, the source included, support the pin's start and end times; a reference counts half as much for every 180 days older than the newestShow all pins at 75% confidence or better2.9 years ago

  Dated Google^[1][2][3] announcement; commercialization milestones are recorded separately in the sourced timeline.

  Google announces its performance-focused fifth-generation TPU, scaling to 8,960-chip pods with 96 GiB of physical HBM per chip, alongside its integrated AI Hypercomputer architecture.

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• Semiconductors11/08/2026@ChipDesk

  Google Introduces TPU v5e for Cost-Efficient AI Training and Inference

  Googleplex, Mountain View, California, United States (company headquarters)Google

  

  Starts 08/29/2023CONFIRMEDDate confidence: CONFIRMEDStated as firmHow firmly the source words the date: confirmed, scheduled, estimated, delayed or unverified.Show all CONFIRMED pins95% CONFIDENCEOverall confidence: 95%How well the pin's source and references back up its dates.Weighted average of how firmly 5 references, the source included, support the pin's start and end times; a reference counts half as much for every 180 days older than the newestShow all pins at 75% confidence or better3.2 years ago

  Dated Google^[1][2][3] announcement; commercialization milestones are recorded separately in the sourced timeline.

  Google launches TPU v5e in preview, targeting medium- and large-scale AI training and inference with 256-chip pods and workload-dependent improvements in performance per dollar.

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• Semiconductors11/08/2026@ChipDesk

  Google Announces TPU v4, Scaling AI Pods Beyond One Exaflop

  Googleplex, Mountain View, California, United States (company headquarters)Google

  

  Starts 05/18/2021CONFIRMEDDate confidence: CONFIRMEDStated as firmHow firmly the source words the date: confirmed, scheduled, estimated, delayed or unverified.Show all CONFIRMED pins95% CONFIDENCEOverall confidence: 95%How well the pin's source and references back up its dates.Weighted average of how firmly 5 references, the source included, support the pin's start and end times; a reference counts half as much for every 180 days older than the newestShow all pins at 75% confidence or better5.5 years ago

  Dated Google^[2][3] announcement; commercialization milestones are recorded separately in the sourced timeline.

  Google unveils TPU v4 at I/O 2021. Its 4,096-chip pods scale beyond one exaflop, while each chip provides 275 BF16 teraflops and 32 GiB of HBM2.

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• Semiconductors11/08/2026@ChipDesk

  Google Introduces TPU v3 With Liquid-Cooled AI Supercomputing

  Googleplex, Mountain View, California, United States (company headquarters)Google

  

  Starts 05/08/2018CONFIRMEDDate confidence: CONFIRMEDStated as firmHow firmly the source words the date: confirmed, scheduled, estimated, delayed or unverified.Show all CONFIRMED pins95% CONFIDENCEOverall confidence: 95%How well the pin's source and references back up its dates.Weighted average of how firmly 5 references, the source included, support the pin's start and end times; a reference counts half as much for every 180 days older than the newestShow all pins at 75% confidence or better8.5 years ago

  The I/O 2018 reveal date is reported by 9to5Google^[5] on May 8, 2018; Google^[1][2] release notes separately date beta and general availability.

  Google introduces its third TPU generation at I/O 2018. Cloud documentation specifies 32 GiB of HBM2 and 123 BF16 teraflops per chip, scaling to 1,024-chip pods.

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• Semiconductors11/08/2026@ChipDesk

  Google Announces TPU v2 and Cloud TPU Training Pods

  Googleplex, Mountain View, California, United States (company headquarters)Google

  

  Starts 05/17/2017CONFIRMEDDate confidence: CONFIRMEDStated as firmHow firmly the source words the date: confirmed, scheduled, estimated, delayed or unverified.Show all CONFIRMED pins95% CONFIDENCEOverall confidence: 95%How well the pin's source and references back up its dates.Weighted average of how firmly 5 references, the source included, support the pin's start and end times; a reference counts half as much for every 180 days older than the newestShow all pins at 75% confidence or better9.5 years ago

  Dated Google^[1][2][3] announcement; commercialization milestones are recorded separately in the sourced timeline.

  Google adds neural-network training to its custom TPU platform, announcing Cloud TPU devices with up to 180 teraflops and interconnected pods for larger workloads.

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• Semiconductors11/08/2026@ChipDesk

  Google Reveals TPU v1, Its First Custom AI Inference Chip

  Googleplex, Mountain View, California, United States (company headquarters)Google

  

  Starts 05/18/2016CONFIRMEDDate confidence: CONFIRMEDStated as firmHow firmly the source words the date: confirmed, scheduled, estimated, delayed or unverified.Show all CONFIRMED pins95% CONFIDENCEOverall confidence: 95%How well the pin's source and references back up its dates.Weighted average of how firmly 13 references, the source included, support the pin's start and end times; a reference counts half as much for every 180 days older than the newestShow all pins at 75% confidence or better10.5 years ago

  Dated Google^{[1][2][4][5][7][8][9][11]} announcement; commercialization milestones are recorded separately in the sourced timeline.

  Google discloses its first Tensor Processing Unit after more than a year of internal use, a custom TensorFlow accelerator already powering Search, Street View and AlphaGo.

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