- Start
- Mar 31, 202090% CONFIDENCEfrom the source
In December last year TSMC started to work on its 5nm process
- TSMC started work on its 5nm process in December 2015, with a target launch of H1 2020, as reported by HEXUS on 6 October 2016[1]
- That report, citing CTimes News, says TSMC has allocated between 300 and 400 R&D staff to develop its 3nm process, to "break the limitation of Moore's law"; President and Co-CEO Dr. Mark Liu said the tool would be three-dimensional stacked architecture technology and that TSMC has established "the complete ecosystems with the intellectual property, automation solutions and equipment providers", and has already earmarked the same 3nm staff to move on to 1nm development[1]
- By 3 April 2019 TSMC announced in Hsinchu that its 5nm process was "already in risk production" and that it had delivered the complete version of its 5nm design infrastructure within the Open Innovation Platform - full Design Rule Manual, SPICE model, PDKs and silicon-validated IP - with customers having "already started intensive design engagements, paving the way for product tape-outs, pilot activities and early sampling"[3]
- Against the 7nm process, TSMC put 5nm at 1.8X logic density and a 15% speed gain on an ARM Cortex-A72 core, helped by process simplification from EUV lithography[3]
- At IEDM in December 2019 TSMC's paper gave ~1.84x logic density increase and a 15% power gain or 30% power reduction, with a 256 Mb SRAM-plus-logic test chip yielding 80% on average and 90%+ at peak, and the densest reported high-density SRAM cell at 21000 nm2 (0.021 um2)[2]
- That newer disclosure confirmed the 2016 target date: "The technology is currently in risk production, with high volume production scheduled for the first half of 2020. This means that chips built on 5nm should be ready in the latter half of 2020."[1][2]
- N5 uses TSMC's 5th generation FinFET and EUV extensively over 10+ layers, which for the first time reduces the number of process masks with a new node - an estimated 75-80 masks versus the 110+ it might have been without EUV; design-technology co-optimisation gave the test chip a 40% chip size reduction, without which it would have been about 25.1 mm2 at 73% yield rather than 80%[2]
- As of the April 2019 release TSMC described its most advanced process in production as 7-nanometer, serving customers with annual capacity of 12 million 12-inch equivalent wafers in 2019 from fabs in Taiwan, the United States and China[3]
References 379% CONFIDENCE
The first entry is always the pin's source. Overall confidence is a weighted average of how firmly each reference supports the start and end times used above; a reference counts half as much for every 180 days older than the newest.
- [1]90%hexus.net/tech/news/industry/97729-tsmc-dedicates-300-boffins-3nm-process-rdhexus.net· Posted Jun 21, 2017· Starts Mar 31, 2020 ✓· 2% of score
Happened as dated, per hexus.net: "…progress of these plans, with a target launch date set for H1 2020. Now a recent report suggests th…"
- [2]80%Early TSMC 5nm Test Chip Yields 80%, HVM Coming in H1 2020anandtech.com· Published Dec 19, 2019· 72% of score
AnandTech's own headline, "Early TSMC[3] 5nm Test Chip Yields 80%, HVM Coming in H1 2020," published December 19, 2019, describes the same H1 2020 volume-manufacturing target the pin's stored 31 March/1 April 2020 date reflects, though published about three months earlier.
- [3]74%TSMC and OIP Ecosystem Partners Deliver Industrys First Complete Design Infrastructure for 5nm Process Technologypr.tsmc.com· Published Apr 3, 2019· 26% of score
TSMC's own press release confirms it delivered a complete 5nm design infrastructure via its Open Innovation Platform on April 3, 2019, with the process already in risk production - about a year ahead of the pin's stored H1 2020 target, consistent with the ramp described in the pin's own reasoning.
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