CONFIRMED79% CONFIDENCEHappened as dated, per hexus.net[1]: "…progress of these plans, with a target launch date set for H1 2020. Now a recent report suggests th…"
In December last year TSMC started to work on its 5nm process. In the following January we heard from the firm's CEO about the progress of these plans, with a target launch date set for H1 2020. Now a recent report suggests that TSMC is confident of reaching its previously publicised goals, as it has started to allocate between 300 and 400 R&D staff to work on developing its 3nm process.
TSMC started work on its 5nm process in December 2015, with a target launch of H1 2020, as reported by HEXUS on 6 October 2016[1]
That report, citing CTimes News, says TSMC has allocated between 300 and 400 R&D staff to develop its 3nm process, to "break the limitation of Moore's law"; President and Co-CEO Dr. Mark Liu said the tool would be three-dimensional stacked architecture technology and that TSMC has established "the complete ecosystems with the intellectual property, automation solutions and equipment providers", and has already earmarked the same 3nm staff to move on to 1nm development[1]
By 3 April 2019 TSMC announced in Hsinchu that its 5nm process was "already in risk production" and that it had delivered the complete version of its 5nm design infrastructure within the Open Innovation Platform - full Design Rule Manual, SPICE model, PDKs and silicon-validated IP - with customers having "already started intensive design engagements, paving the way for product tape-outs, pilot activities and early sampling"[3]
Against the 7nm process, TSMC put 5nm at 1.8X logic density and a 15% speed gain on an ARM Cortex-A72 core, helped by process simplification from EUV lithography[3]
At IEDM in December 2019 TSMC's paper gave ~1.84x logic density increase and a 15% power gain or 30% power reduction, with a 256 Mb SRAM-plus-logic test chip yielding 80% on average and 90%+ at peak, and the densest reported high-density SRAM cell at 21000 nm2 (0.021 um2)[2]
That newer disclosure confirmed the 2016 target date: "The technology is currently in risk production, with high volume production scheduled for the first half of 2020. This means that chips built on 5nm should be ready in the latter half of 2020."[1][2]
N5 uses TSMC's 5th generation FinFET and EUV extensively over 10+ layers, which for the first time reduces the number of process masks with a new node - an estimated 75-80 masks versus the 110+ it might have been without EUV; design-technology co-optimisation gave the test chip a 40% chip size reduction, without which it would have been about 25.1 mm2 at 73% yield rather than 80%[2]
As of the April 2019 release TSMC described its most advanced process in production as 7-nanometer, serving customers with annual capacity of 12 million 12-inch equivalent wafers in 2019 from fabs in Taiwan, the United States and China[3]
The first entry is always the pin's source. Overall confidence is a weighted average of how firmly each reference supports the start and end times used above; a reference counts half as much for every 180 days older than the newest.
anandtech.com· Published Dec 19, 2019· 72% of score
AnandTech's own headline, "Early TSMC[3] 5nm Test Chip Yields 80%, HVM Coming in H1 2020," published December 19, 2019, describes the same H1 2020 volume-manufacturing target the pin's stored 31 March/1 April 2020 date reflects, though published about three months earlier.
TSMC's own press release confirms it delivered a complete 5nm design infrastructure via its Open Innovation Platform on April 3, 2019, with the process already in risk production - about a year ahead of the pin's stored H1 2020 target, consistent with the ramp described in the pin's own reasoning.
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DELAYED12 months late67% CONFIDENCEin 1.3 yearsTSMC's[2][5] Kevin Zhang told Tom's Hardware "A16 will be ready for production in 2026... we expect volume production to begin in 2027", and TSMC's roadmap slide lists A16 under 2027; with no quarter named, the year's last day stands in.
A16, TSMC's first node with Super Power Rail backside power delivery, is expected to reach volume production in 2027, a year after the 2026 production TSMC planned when it unveiled the node.
ESTIMATED73% CONFIDENCE266 days agoTSMC's[1][2] 2nm page says N2 "has started volume production in 4Q25 as planned" and its 2025 annual report that it "entered high volume manufacturing in 4Q'25"; neither names the day, so the quarter's last day stands in.
TSMC's first nanosheet-transistor node, N2, entered volume production in the fourth quarter of 2025 as planned, starting at Fab 22 in Kaohsiung, with Fab 20 in Hsinchu as its second 2nm fab.
ESTIMATED12 months late71% CONFIDENCEin 2.3 yearsOnly a year is given: Taiwan's MOEA says the fab is "scheduled to start installing equipment and come online in 2028", and C.C. Wei said on the 16 April 2026 call that "commercial production is scheduled to begin in 2028" - so the year's last day, estimated.[1]
JASM's second fab in Kikuyo, Kumamoto - switched from 6nm-class chips to TSMC's 3nm process - is due to start volume production in 2028 at 15,000 12-inch wafers a month, making Japan's first 3nm chips about a year after the end-2027 start TSMC first promised.
CONFIRMED85% CONFIDENCE154 days agoTSMC's[1] release is datelined "SANTA CLARA, CA, Apr. 22, 2026" and says it "today debuted" A13 at the symposium; GUC's event page gives "8:30 a.m. - 5:30 p.m. (PDT, UTC-7)" at the Santa Clara Convention Center.
TSMC's largest annual customer event opened its 2026 series at the Santa Clara Convention Center on 22 April, where it debuted the A13 process, previewed A12 and introduced N2U.
CONFIRMED85% CONFIDENCE1.1 years agoThe Intellectual Property Branch's own release, posted 114-08-27 (27 August 2025), says the case against the three detained defendants 'was concluded today (27th)' ('於今（27）日偵查終結') and an indictment filed; no time is given, so it is an all-day date.[1]
Prosecutors charged former TSMC engineer Chen Li-ming, by then at Tokyo Electron's Taiwan unit, and two serving TSMC engineers with stealing 2nm trade secrets, seeking 14, 9 and 7 years in Taiwan's first indictment for theft of a national core key technology.
CONFIRMED87% CONFIDENCE149 days agoFocus Taiwan[1] (CNA[3][4][5]), 27 April 2026: 'A former TSMC engineer has been sentenced to 10 years in prison ... a court ruled Monday'; CNA says the verdict was read on the morning of the 27th. No time is given, so it is an all-day date.
Taiwan's Intellectual Property and Commercial Court jailed Chen Li-ming for 10 years, three TSMC engineers for 2 to 6 years, and fined Tokyo Electron's Taiwan unit NT$150 million - the first verdict under the National Security Act's core-technology clause.
SCHEDULED80% CONFIDENCEin 22 daysTSMC's[1][2][3] own teleconference notice reads "TSMC Third Quarter 2026 Earnings Conference Call ... Thursday, October 15, 2026, 02:00 - 03:30 a.m. Eastern Time / 14:00 - 15:30 p.m. Taiwan Time", so 06:00-07:30 UTC; the notice names no venue yet, so the pin sits at TSMC's headquarters.
TSMC reports third-quarter 2026 results and gives its fourth-quarter outlook at its earnings conference on Thursday 15 October at 2 p.m. Taiwan time, against its own guidance of US$44.6-45.8 billion in revenue and a 65-67% gross margin.
ESTIMATED58% CONFIDENCEin 3.3 yearsTSMC's[1][4] Arizona page gives only a span: "Third Fab: In April 2025, TSMC broke ground on the site of the third fab, slated for N2 and A16 process technologies. Targeting volume production by the end of the decade." - so the decade's last day, estimated.
The third fab on TSMC's north Phoenix campus, where ground was broken in April 2025, is slated for its 2nm (N2) and A16 processes and targeted for volume production by the end of the decade - the most advanced chipmaking TSMC has committed to the United States.
CONFIRMED86% CONFIDENCE251 days agoCNBC[1], published 15 January 2026: 'The U.S. and Taiwan have reached a trade agreement ... the Department of Commerce announced Thursday'; USTR's[2] February fact sheet dates the 'Memorandum of Understanding signed by AIT and TECRO on January 15, 2026'. No signing time is given, so it is an all-day date.
A memorandum signed in Washington commits Taiwanese chipmakers such as TSMC to at least $250 billion of new US investment plus $250 billion in Taiwan credit guarantees, in return for a 15% tariff cap and Section 232 chip-tariff exemptions for companies building US fabs.
ESTIMATED73% CONFIDENCEin 1.3 yearsTSMC's[1][6] founding release gives a bound, not a day: "production targeted to begin by the end of 2027"; at the September 2026 topping-out the partners still said production starts in 2027 and Hardwareluxx[3] reported tool installation "bis Ende 2027", after which the first chips follow - so 31 December 2027, estimated.
ESMC, TSMC's EUR 10 billion joint venture with Bosch, Infineon and NXP, is due to start production at its Dresden fab by the end of 2027 - Europe's first FinFET-capable foundry, making 28/22nm and 16/12nm chips mainly for cars and industry.
SCHEDULED80% CONFIDENCETodayTSMC's[2][3] OIP site lists "Date: Wednesday, September 23, 2026 Time: 9:30am - 6pm (Pacific Standard Time) Venue: Santa Clara Convention Center, CA" (Pacific daylight time in September, UTC-7); TSMC's events page lists 2026/09/23 Santa Clara.
TSMC's 18th Open Innovation Platform Ecosystem Forum brings chip designers, EDA and IP partners and customers to the Santa Clara Convention Center on 23 September, opening a global series that ends in Israel in December.
CONFIRMED86% CONFIDENCE69 days agoTSMC's[1][2] release, datelined "HSINCHU, Taiwan, R.O.C., Jul. 16, 2026", says TSMC "today announced" its second-quarter results, and the call transcript TSMC posts gives "EVENT DATE/TIME: JULY 16, 2026 / 6:00AM GMT" (2 p.m. Taiwan time, as the FTNN report of TSMC's schedule says: "16日下午2時").
TSMC reported second-quarter revenue of US$40.20 billion, up 33.7% from a year earlier, a 67.7% gross margin and record net income of NT$706.56 billion, guided Q3 revenue to US$44.6-45.8 billion and raised its 2026 capital budget to US$60-64 billion.
