Pins matching tag:"AI Accelerators"

Google discloses its first Tensor Processing Unit after more than a year of internal use, a custom TensorFlow accelerator already powering Search, Street View and AlphaGo.

Google adds neural-network training to its custom TPU platform, announcing Cloud TPU devices with up to 180 teraflops and interconnected pods for larger workloads.

Google introduces its third TPU generation at I/O 2018. Cloud documentation specifies 32 GiB of HBM2 and 123 BF16 teraflops per chip, scaling to 1,024-chip pods.

Google unveils TPU v4 at I/O 2021. Its 4,096-chip pods scale beyond one exaflop, while each chip provides 275 BF16 teraflops and 32 GiB of HBM2.

Google launches TPU v5e in preview, targeting medium- and large-scale AI training and inference with 256-chip pods and workload-dependent improvements in performance per dollar.

Google announces its performance-focused fifth-generation TPU, scaling to 8,960-chip pods with 96 GiB of physical HBM per chip, alongside its integrated AI Hypercomputer architecture.

Intel introduced the Gaudi 3 AI accelerator on April 9, 2024 at Intel Vision, a 5 nm part with 24 on-board 200 Gb Ethernet ports that Intel pitched against Nvidia's H100 for enterprise generative AI.

Google announces Trillium (TPU v6e), with 4.7 times the peak compute per chip of TPU v5e, double its HBM capacity and a claimed improvement of over 67% in energy efficiency.

Google announces Ironwood for large-scale inference, later documented as TPU7x for both training and inference, with 192 GiB of HBM per chip and pods of up to 9,216 chips.

Google announces the training-focused half of its eighth TPU generation: 9,600-chip superpods, native FP4, 216 GB of HBM per chip and Axion hosts. The current product page lists it as coming soon.

Google announces its inference-focused eighth-generation TPU, combining 288 GB of HBM, 384 MB of on-chip SRAM and Boardfly networking across up to 1,152 chips. Availability is still listed as coming soon.